There are many ways to solve EMI problems. Modern EMI suppression methods include: using EMI suppression coating, selecting appropriate EMI suppression parts and components, EMI simulation design, etc. Starting from the most basic PCB layout, this paper discusses the function and design skills of PCB layered stacking in controlling EMI radiation.
Power bus
If a capacitor with appropriate capacity is reasonably placed near the power supply pin of the IC, the output voltage of the IC can jump faster. However, the problem does not end there. Due to the characteristic of finite frequency response of the capacitor, it can’t generate the harmonic power needed to drive IC output cleanly in the whole frequency band. In addition, the transient voltage formed on the power bus will form a voltage drop across the inductance of the decoupling path, and these transient voltages are the main common-mode EMI interference sources. How should we solve these problems?
As far as the IC on our circuit board is concerned, the power layer around the IC can be regarded as an excellent high-frequency capacitor, which can collect the part of the energy leaked from the discrete capacitor that provides high-frequency energy for clean output. In addition, the inductance of an excellent power supply layer should be small, so the transient signal synthesized by the inductance is also small, thus reducing the common-mode EMI.
Of course, the connection between the power supply layer and the IC power supply pin must be as short as possible, because the rising edge of the digital signal is faster and faster, and it is better to connect it directly to the pad where the IC power supply pin is located, which will be discussed separately.
In order to control the common-mode EMI, the power supply layer should contribute to decoupling and have low enough inductance, and this power supply layer must be a well-designed power supply layer. Some people may ask, how good is it? The answer depends on the layers of power supply, the materials between layers and the working frequency (i.e. the function of IC rise time). Generally, the spacing of power supply layers is 6mil, and the interlayer is made of FR4 material, so the equivalent capacitance per square inch of power supply layer is about 75pF. Obviously, the smaller the layer spacing, the greater the capacitance.
There are not many devices with a rise time of 100 to 300ps, but according to the current IC development speed, devices with a rise time of 100 to 300ps will occupy a high proportion. For circuits with a rise time of 100 to 300ps, 3mil layer spacing will no longer be suitable for most applications. At that time, it is necessary to adopt the layering technology with the layer spacing less than 1mil, and replace the FR4 dielectric material with the material with high dielectric constant. At present, ceramics and potting plastics can meet the design requirements of 100 to 300ps rise time circuits.
Although new materials and methods may be adopted in the future, today’s common 1-3ns rise-time circuits, 3-6mil interlayer spacing and FR4 dielectric materials are usually enough to handle high-end harmonics and make transient signals low enough, that is, common-mode EMI can be reduced very low. The example of PCB layered stacking design given in this paper will assume that the layer spacing is 3 to 6 mils.
electromagnetic shielding
From the point of view of signal routing, a good layering strategy should be to place all signal routing on one or several layers, which are next to the power layer or the ground layer. For power supply, a good layering strategy should be that the power supply layer is adjacent to the ground layer, and the distance between the power supply layer and the ground layer is as small as possible, which is what we call “layering” strategy.
PCB stack
What kind of stacking strategy helps to shield and suppress EMI? The following layered stacking scheme assumes that the power supply current flows on a single layer, and single or multiple voltages are distributed in different parts of the same layer. The situation of multiple power layers will be discussed later.
4-layer board
There are some potential problems in 4-ply design. First of all, the traditional four-layer board with a thickness of 62mil, even if the signal layer is on the outer layer and the power and ground layers are on the inner layer, the distance between the power layer and the ground layer is still too large.
If the cost requirement is the first, the following two alternatives of traditional 4-layer board can be considered. Both schemes can improve the performance of EMI suppression, but they are only suitable for the situation where the density of components on the board is low enough and there is enough area around the components (to place the required copper-clad layer of power supply).
The first is the preferred scheme, in which the outer layers of PCB are all ground layers and the middle two layers are signal/power layers. The power supply on the signal layer is routed with wide wires, which can make the path impedance of the power supply current low, and the impedance of the signal microstrip path is also low. From the point of view of EMI control, this is the best existing 4-layer PCB structure. In the second scheme, the outer layer is connected with the power supply and the ground, and the middle two layers are connected with the signal. Compared with the traditional 4-layer board, the improvement of this scheme is smaller, and the interlayer impedance is as poor as the traditional 4-layer board.
If the impedance of the wiring is to be controlled, all the above stacking schemes should carefully arrange the wiring under the copper island of power supply and grounding. In addition, the power supply or copper-plated islands on the ground should be interconnected as much as possible to ensure the connectivity between DC and low frequency.
6-layer board
If the density of components on the 4-layer board is relatively high, it is best to use the 6-layer board. However, some lamination schemes in 6-layer board design are not good enough to shield electromagnetic field, and have little effect on reducing transient signal of power bus. Two examples are discussed below.
In the first example, the power supply and the ground are placed on the 2nd and 5th floors respectively, which is very unfavorable to control the common-mode EMI radiation due to the high impedance of the copper-clad power supply. However, from the point of view of signal impedance control, this method is very correct.
In the second example, the power supply and the ground are placed on the 3rd and 4th floors respectively. This design solves the problem of copper-clad impedance of the power supply. Due to the poor electromagnetic shielding performance of the 1st and 6th floors, the differential mode EMI increases. This design can solve the problem of differential mode EMI if the number of signal lines on the two outer layers is the least and the trace length is very short (shorter than 1/20 of the highest harmonic wavelength of the signal). The suppression of differential-mode EMI is particularly good when the areas without components and traces on the outer layer are filled with copper and the copper-clad areas are grounded (every 1/20th wavelength interval). As mentioned above, the copper plating area should be connected with the internal grounding layer at multiple points.
In the general design of high-performance 6-layer board, the first and sixth layers are generally arranged as strata, and the third and fourth layers are connected with power supply and ground. Because there are two intermediate double microstrip signal lines between the power layer and the ground layer, the EMI suppression ability is excellent. The disadvantage of this design is that there are only two wiring layers. As mentioned earlier, if the outer wiring is short and copper is laid in the area without wiring, the same stacking can be achieved with the traditional 6-layer board.
Another 6-layer board layout is signal, ground, signal, power, ground and signal, which can realize the environment required by advanced signal integrity design. The signal layer is adjacent to the ground layer, and the power layer and the ground layer are paired. Obviously, the deficiency is the unbalanced stacking of layers.
This usually brings trouble to manufacturing. The solution to the problem is to fill all the blank areas of the third layer with copper. After filling copper, if the copper density of the third layer is close to the power layer or the ground layer, this board can be loosely regarded as a circuit board with balanced structure. Copper filling area must be connected to power supply or ground. The distance between connecting vias is still 1/20th wavelength, so it is not necessary to connect everywhere, but ideally it should be.
10-layer board
Because the insulation layer between the multilayer boards is very thin, the impedance between the layers of the 10-or 12-layer circuit board is very low. As long as there are no problems in layering and stacking, excellent signal integrity can be expected. There are many difficulties in manufacturing 12-ply board with the thickness of 62mil, and there are not many manufacturers that can process 12-ply board.
Because there is always an insulating layer between the signal layer and the loop layer, it is not the best scheme to allocate the middle 6 layers to take the signal line in the 10-layer board design. In addition, it is important to make the signal layer adjacent to the loop layer, that is, the board layout is signal, ground, signal, power, ground, signal, signal, ground and signal.
This design provides a good path for signal current and its loop current. The proper wiring strategy is that the first layer runs along the X direction, the third layer runs along the Y direction, the fourth layer runs along the X direction, and so on. Intuitively, the first and third floors are a pair of layered combinations, the fourth and seventh floors are a pair of layered combinations, and the eighth and tenth floors are the last pair of layered combinations. When it is necessary to change the routing direction, the signal lines on the 1st floor should go through the “via hole” to the 3rd floor before changing the direction. Actually, it may not always be possible to do this, but as a design concept, we should try our best to follow it.
Similarly, when the routing direction of the signal changes, it should go from the 8th and 10th floors or from the 4th floor to the 7th floor through vias. This ensures the tightest coupling between the forward path of the signal and the loop. For example, if the signal is routed on the first layer and the loop is routed on the second layer only, then even if the signal on the first layer is transferred to the third layer by “via hole”, its loop is still on the second layer, thus maintaining the characteristics of low inductance, large capacitance and good electromagnetic shielding performance.
What if the actual route is not like this? For example, if the signal line on the 1st floor goes to the 10th floor via a via hole, then the loop signal has to find the ground plane from the 9th floor, and the loop current has to find the nearest ground via hole (such as the grounding pin of resistor or capacitor). If such a via happens to exist nearby, it is really lucky. If there is no such close via available, the inductance will become larger, the capacitance will decrease, and the EMI will definitely increase.
When the signal line has to leave the current pair of wiring layers to other wiring layers via vias, the grounding via should be placed near the via, so that the loop signal can smoothly return to the appropriate grounding layer. For the layered combination of the 4th and 7th layers, the signal loop will return from the power layer or the ground layer (i.e. the 5th or 6th layer), because the capacitive coupling between the power layer and the ground layer is good and the signal is easy to transmit.
Design of multiple power supply layers
If two power layers of the same voltage source need to output large current, the circuit board should be arranged into two groups of power layers and ground layers. In this case, an insulating layer is placed between each pair of power layers and ground layers. In this way, two pairs of power buses with equal impedance, which are expected to divide the current equally, are obtained. If the stack of power layers causes unequal impedance, the shunt will be uneven, the transient voltage will be much larger, and the EMI will increase sharply.
If there are multiple power supply voltages with different values on the circuit board, multiple power supply layers are needed accordingly. It should be remembered to create respective paired power supply layers and ground layers for different power supplies. In the above two cases, when determining the position of the paired power plane and ground plane on the circuit board, keep in mind the manufacturer’s requirements for the balanced structure.
summary
Since the circuit boards designed by most engineers are traditional printed circuit boards with a thickness of 62mil and no blind holes or buried holes, the discussion on circuit board layering and stacking in this paper is limited to this. The layered scheme recommended in this paper may not be ideal for circuit boards with too large thickness difference. In addition, the processing process of circuit boards with blind holes or buried holes is different, so the layering method in this paper is not applicable.
Thickness, via process and the number of layers in circuit board design are not the key to solve the problem. Excellent layered stacking is the key to ensure the bypass and decoupling of the power bus, minimize the transient voltage on the power layer or ground layer and shield the electromagnetic field of the signal and power supply. Ideally, there should be an insulation layer between the signal wiring layer and its return grounding layer, and the distance between the paired layers (or more than one pair) should be as small as possible. According to these basic concepts and principles, we can design circuit boards that can always meet the design requirements. Now, the rising time of IC has been very short and will be shorter, and the technology discussed in this paper is essential to solve the EMI shielding problem.
