There is an appropriate capacitor near the power supply pin of the ic, and the output voltage of the IC can jump quickly. However, the problem will not stop there. Because of the characteristic of finite frequency response, the capacitor can’t produce the harmonic power needed to drive the full-band IC output cleanly. In addition, the voltage drop across the decoupling path caused by the transient voltage on the power bus is the main cause of common-mode EMI interference. How should these problems be solved?
Compared with the circuit board on the IC, the power supply layer of the peripheral IC is regarded as an excellent high-frequency capacitor for recovering some energy from the discrete capacitor and leaking to the high-frequency energy provided by the clean output. Furthermore, because the inductance of the excellent power layer is small and the inductance of the synthesized transient signal is also small, the common-mode EMI is reduced.
Of course, the wiring from the power supply layer to the IC power supply pins is a faster rise of digital signals. As it is better to directly connect to the pad IC power supply pins, it is necessary to describe them separately, and keep them as short as possible as you must.
In order to control the common-mode EMI as a decoupled power supply layer, it is necessary to have a sufficiently low inductance, and it must be designed as a power supply layer in pairs. Some people may ask, how good is it? The answer to this question depends on the hierarchical structure of the power supply, the materials between layers and the working frequency (a function of the rise time of IC). Generally, the distance between power layers is 6 mils, the interlayer is made of FR4 material, and the equivalent capacitance per square inch of power level is about 75 pF. Obviously, the smaller layer spacing is the larger capacitance.
The 300PS 100 rising time of this device is not much, and according to the current development speed of IC, the rising time in the range of 100〜300PS accounts for a high proportion. Circuits with a rise time of 100 to 300 ps will not impose a 3 mil interval on most applications. At this time, it is necessary to use a high dielectric constant material instead of FR4 dielectric material when the interlayer spacing is less than 1 mil. At present, ceramic and ceramic plastics can meet the design requirements of 100 ps and 300 ps rise time circuit.
New materials and methods, but they are all used in the future. It is enough to deal with harmonics at high end and make the transient signal low enough, that is, the common-mode EMI may drop very low, for the usual single-day interval and the rise time circuit of FR4 dielectric material 6mil 3 is 3ns. In this paper, the PCB laminate design example assumes that the layer spacing is 3 to 6 mils.
