The package plays the role of installation, fixation, sealing, chip protection and electric heating performance enhancement. In addition, according to the contacts on the chip, the pins are connected to the pins of the packaging case by power lines, and the pins are connected with other components according to the power lines on the printed circuit board, thus completing the connection between the internal chip and the external power circuit.
Therefore, the chip must be protected from the outside, so as to avoid the erosion of the chip power supply circuit by residues in the air, resulting in the performance degradation of electrical equipment. And the packaged chip is more convenient for installation and transportation. Because the advantages and disadvantages of packaging immediately endanger the full performance of the chip itself and the PCB design and manufacturing connected with it, packaging technology is particularly important.
The key index value to consider whether a chip package technology is excellent is the ratio of total chip area to total package area. The closer this ratio is to 1, the better.
Key factors to consider when packaging:
The ratio of the total chip area to the total package area should be as close to 1:1 as possible to improve the package efficiency.
The pins should be as short as possible to reduce the delay time, and the spacing between pins should be as far as possible to ensure mutual influence and improve performance.
According to the regulation of heat pipe heat dissipation, the thinner the package, the better.
Packaging has probably gone through the following development trends:
Structure.
TO→DIP→PLCC→QFP→BGA→CSP。
Raw materials. Materials, porcelain → porcelain, plastic → plastic.
Pin appearance. Long wire insertion → short wire or no wire patch → spherical bump.
Installation method. Buried hole insertion → surface assembly → immediate installation.
The following is a detailed description of the actual packaging method:
SOP/SOIC package
SOP shows the abbreviation of English SmallOutlinePackage, that is, small design package.
SOP package
SOP packaging technology was successfully developed and designed by Philips Enterprises in 1968 ~ 1969, and then developed slowly:
SOJ, j-pin small appearance design package
TSOP, thin and small design package
VSOP, very small design package
SSOP, small SOP
TSSOP, thin and small SOP
SOT, small design triode
SOIC, small design integrated circuit chip
dual in line package
DIP shows the abbreviation of “DoubleIn-linePackage” in English, that is, double-row straight plug-in package.
dual in line package
One of plug-in packages, the pins are led out from both sides of the package, and the packaging raw materials are plastic and porcelain. DIP is the most popular plug-in package, and its application scope includes standard logic IC, memory LSI, microcomputer power supply circuit, etc.
plastic leaded chip carrier
PLCC shows the abbreviation of “PlasticLeadedChipCarrier” in English, that is, plastic J-wire chip package.
plastic leaded chip carrier
PLCC packaging method, the design is square, 32-pin package, with pins all around, and the size is much smaller than that of DIP package. PLCC package is suitable to use SMT surface mounting technology to install wiring on PCB, which has the advantages of small size and high reliability.
04TQFP package
TQFP shows the abbreviation of “ThinQuadFlatPackage” in English, that is, thin plastic package with flat corners. Four-sided flat packaging processing technology can reasonably use indoor space, thus reducing the regulations on indoor space size of printed circuit boards.
thin quad flat package
Because of the reduced aspect ratio and volume, this kind of packaging technology is especially suitable for applications with high requirements for indoor space, such as PCMCIA cards and Internet components. Basically, all the CPLD/FPGA of ALTERA have TQFP package.
PQFP package
PQFP shows the abbreviation of “PlasticQuadFlatPackage” in English, that is, plastic package with flat corners.
PQFP package
The chip pins in PQFP package have small spacing between them, and the pins are very thin. General scale or integrated circuit technology integrated circuit chips use this kind of packaging method, and the number of pins is generally more than 100.
thin small outline package
TSOP shows the abbreviation of “ThinSmallOutlinePackage” in English, that is, thin small specification package. A typical feature of TSOP running memory packaging technology is to make pins around the packaging chip. TSOP is suitable to use SMT (Surface Mount) technology to install wiring on PCB.
thin small outline package
TSOP package design, parasitic parameters (output voltage oscillation caused by large change of current) are reduced, so it is suitable for high frequency application, practical operation is more convenient, and credibility is higher.
ball grid array package
Shows the abbreviation of BGA “BallGridArrayPackage”, that is, ball grid array package. In the 1990s, with the development of technology, the processing speed of chips has been continuously improved, the number of I/O pins has been greatly increased, the power has also been expanded, and the requirements for IC chip packaging have become more stringent. In order to consider the development trend, BGA package has just been used in manufacturing.
ball grid array package
Using BGA technology to package the running memory can increase the memory space by two to three times without changing the memory volume. Compared with TSOP, BGA has smaller volume, stronger heat pipe heat dissipation and electrical performance. BGA packaging technology has greatly improved the storage capacity per square inch. Under the same volume, the volume of running memory products using BGA packaging technology can only be one-third of TSOP packaging. In addition, compared with the traditional TSOP packaging method, BGA packaging method has a more rapid and reasonable heat pipe heat dissipation method.
I/O terminals of BGA package are distributed under the package in the form of array by ring or column spot welding. The advantage of BGA technology is that although the number of I/O pins has been increased, the pin spacing has been increased instead of decreased, thus improving the assembly yield. Although its power is increased, BGA can be welded by controllable collapse chip method, which can improve its electrothermal performance. Compared with the previous packaging technology, the thickness and net weight are reduced to some extent; Parasitic parameters are reduced, data signal transmission delay time is short, and application frequency is further improved; Can be assembled and welded by coplanar electric welding, and has high credibility.
TinyBGA package
When it comes to BGA packaging, we must mention TinyBGA technology, the patent of Kingmax. TinyBGA is called “TinyBallGrid” in English, which belongs to a branch of BGA packaging technology. It was successfully developed and designed by Kingmax in August 1999. The ratio of the total chip area to the total package area is not less than 1:1.14, which can increase the memory space by 2 ~ 3 times without changing the memory volume. Compared with TSOP package products, it has smaller volume, stronger heat pipe heat dissipation performance and electrical performance.
Under the same volume condition, the volume of running memory products with TinyBGA package technology can only be 1/3 of that of TSOP package. The pins of TSOP package running memory are led out from the periphery of the chip, while TinyBGA is led out from the direction of the chip management center. This kind of method reasonably reduces the transmission distance of data signal, and the length of coaxial cable of data signal is only 1/4 of that of traditional TSOP technology, so the attenuation coefficient of data signal also decreases. That not only greatly improves the anti-interference and anti-noise performance of the chip, but also improves the electrical performance. TinyBGA package chip can resist external frequency up to 300MHz, while traditional TSOP package technology can only resist external frequency up to 150MHz.
In the operation of TinyBGA package, its thickness is also thinner (the aspect ratio of the package is lower than 0.8mm), and the reasonable heat pipe heat dissipation relative path from the metal-based steel plate to the heat pipe radiator is only 0.36mm. Therefore, TinyBGA running memory has higher thermal conductivity and high efficiency, which is very suitable for long-term running system software and has excellent reliability.
quad flat package
QFP is the abbreviation of “QuadFlatPackage”, that is, small and medium-sized lattice plan package. QFP package is often used in the initial discrete graphics card, but the memory of QFP package graphics card with a bit rate above 4ns has been gradually replaced by TSOP-II and BGA at this stage due to the difficulties of processing technology and performance. QFP package contains needle corners all around the particles, which is very obvious for identification. Four-pin flat package. One of the surface-mounted packages, the pins are led out from four sides in a red-billed gull wing (L) shape.
quad flat package
There are three kinds: plate porcelain, metal material and plastic. From the total point of view, plastic packaging accounts for the vast majority. When the raw materials are not very clear, most of them are plastic QFP. Plastic QFP is the most popular multi-pin LSI package, which is not only used for digital logic LSI power circuits such as microcontroller and door display design, but also used for VTR signal analysis and speaker signal analysis.
The distance between pin management centers is 1.b250m, 0.8mm, 0.65mm, 0.0mm, 0.4mm, 0.2mm, etc. The maximum number of pins in the 0.65mm management center is 304.
