Hai si series hi3521A hardware design user manual, Hi3521A chip data reference
1.SchematicDiagramDesign
1.1ExternalCircuitsfortheSmallsystem
1.1.1ClockingCircuit
By combining the internal feedback circuit of Hi3521A with the external crystal oscillator circuit of 24mhz, the system clock circuit can be generated.
Hi3521A integrates a real-time clock (RTC). A clock circuit must be provided for the RTC on the board.
Hi3521a selects internal reset mode or external reset mode by checking the state of POR_enable pin during startup.
The AB19 pin supports WDGRSTN and SYSRSTNOUT functions. When Hi3521A uses the internal reset mode, the Ab19 pin is multiplexed into the SYS_RSTn_OUT function. When HI351A uses external reset mode, AB19 pin is multiplexed into WDG_RSTn function.
-When the AB19 pin is multiplexed as a WDG_RSTn function, it must be connected to an external pull-up resistor because it is an open drain (OD) output pin.
-When the level of POR_ENABLE is high, select the internal reset mode. After the main chip is powered on, the internal power-on reset (POR) circuit resets the chip, and when the AB19 pin is multiplexed as the SYS_RSTN_OUT function, it outputs a reset signal to reset the related peripheral devices.
-The reset time falls within 100 or 300 ms. The AB19 pin is multiplexed into the WDG_RSTn function.
-In the board-level design, if the external reset mode is selected, a dedicated reset chip can be used to generate the reset signal. The watchdog takes effect, and the WDG_RSTN pin continuously outputs a low level and returns to a high level until the RSTN pin detects a low level reset signal. Therefore, the WDG_RSTN pin can be connected to the input pin of the external reset chip to reset the whole system.
