Loongson 2H development board adopts SOC chip design and test.

There are two kinds of SRAM in Loongson chip: one is CPUSRAM； which is closely related to microprocessor (data, code memory); The other is HDCSRAM used for hard disk control, which can’t be read directly by microcontroller, and is a dual-port SRAM. Both of them choose different testing strategies.
Test strategy of CPUSRAM
Like the dense SRAM, the layout of SRAM macro cells is also upgraded by hand, which can continuously approach the process limit and save space and energy consumption. In order to get higher productivity, redundant cells are added to the dense SRAM. So as to reduce the test cost and minimize the inserted circuit. Most of the tests are stimulated by the above DRAM memory, and can be directly tested on the memory tester. Considering that the SRAM test should be operated on the memory tester, the test optimization algorithm of the microcontroller reading the memory control module SRAM is stored in a ROM called MSIST (Memory Self-Check Mobile Phone Software) when designing the scheme. This program flow can not only be easily controlled by the memory tester, but also can be easily changed by the single-sided mask redesign scheme. Through that DFT design scheme, all the memory tests can be carried out on a special memory tester, and then the redundant memory can be fused. MSIST and MBIST can implement march-14, flag test and anti-flag test.
BIST Mobile Phone Software Testing with Dual-port SRAM
HDC dual-port SRAM which can’t be directly read by CPU in ic is tested by download application through BIST optimization algorithm operated by CPU. Because the test method of mobile phone software is selected, it is necessary to prepare the test space vector of mobile phone software in advance. When designing the scheme, the layout of SRAM and the creation of MBIST logic on it should be taken into account.
For most SRAM, the operation speed of MBIST can be stored in the same way and speed, while the hardware configuration MBIST is often integrated after a lower speed or changes. Therefore, it is not easy to use the mobile phone software method, such as RAM passing in the test, but invalid in the specific application.
DFM
When testing, it should be considered to establish a bit invalid map (BFM) for all SRAM, which can be output through the data line of CPU. This kind of invalid diagram is very important for production and processing, and it can show extremely important and necessary information to process engineers at the level of scientific research and improvement of compliance rate.
Testing RAM
In the past two years, the testing of embedded DRAM has been the focus of attention. The pre-fusing test is added from the pin by special logic. The external memory of ATE shows the comparison of all incentives and expected results, and ATE creates BFM for invalid units and calculates the best repair plan. DRAM has the ability to build redundant measurement, that is, BISR (Built-in Self-Repair).
Construction of DRAM with High Parallel Test
Generally, the test time occupied by DRAM is longer than that of logic test. So as to reduce the reasonable test time of individual components, and the high parallel test is considered in the design scheme.
Pre-fuse test of embedded DRAM is carried out on a dedicated memory tester, using BIST direct way. In that way, the test time is reduced by reducing the time calculation of redundancy repair and high parallel testing. The advantages of a special-purpose memory tester are: the hardware configuration is suitable for memory test optimization algorithm, it can store and analyze the bit invalid information of a detailed multi-megabit memory, and it can show a lot of power supply for high parallel testing.
This component is tested by memory ATE. Therefore, it is necessary to introduce (prepare the coding sequence in advance) the structural memory with a minimum test method. Once the memory structure is good, it is necessary to show a typical memory socket, including the input and output of redundant data. By limiting the total number of detailed addresses and data typing, and dividing the required pins on the two opposite edges of the integrated ic, high parallel testing can be completed.
Test of DRAM with BIST
The DRAM control module with BIST control board can be activated after the IEEEll49．1 command is properly laid out. Once the fuse has just started, DRAM testing must take into account the repair of the memory professionally, and can be carried out on the standard logical ATE. Because BIST generates detailed address and control data signals from above, and only sends out a pass/fail result. Therefore, the number of ports used for connection will be greatly reduced. As a Chinese independent brand, Loongson 2H adopts SoC design, integrated CPU, GPU North Bridge and South Bridge chips. The low power consumption scheme is adopted, and the characteristic functions of reducing energy consumption include manual clock gating and power supply | voltage regulator management functions, such as module-level clock gating method, CPU frequency adjustment, CPU temperature sensing, etc. In terms of specifications, Loongson 2H is based on MIPS64 instruction set, which can run under multiple operating systems. It consumes 4W at 1GHz, and is equipped with 64KB (data) /64KB (instruction) L1 cache connected by 4-way groups. The second-level cache is 512KB, while Vivante’s GC800 GPU is used for graphics, which is adopted by Ruixinwei’s new generation RK2918 chip. According to the data published by Vivante, GC800 GPU is based on unified architecture, supports OpenGL ES 2.0 and 40nm LP process version, provides polygon generation rate of 31.5M/s, pixel generation rate of 315M/s, and the product supports 1080p video playback.